A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver
- Matt Park
- John Bulzacchelli
- et al.
- 2007
- ISSCC 2007
Publications
11 results at ISSCC 2007
A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI
- A. Rylyakov
- J. Tierno
- et al.
- 2007
- ISSCC 2007
Gate work function engineering for nanotube-based circuits
- Zhihong Chen
- Joerg Appenzeller
- et al.
- 2007
- ISSCC 2007
A 70GHz manufacturable complementary LC-VCO with 6.14GHz tuning range in 65nm SOI CMOS
- Daeik D. Kim
- Jonghae Kim
- et al.
- 2007
- ISSCC 2007
Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- ISSCC 2007
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
Design of the Power6™ microprocessor
- Joshua Friedrich
- Bradley McCredie
- et al.
- 2007
- ISSCC 2007
All-digital dynamic self-detection and self-compensation of static phase offsets in charge-pump PLLs
- Liu Yong
- Woogeun Rhee
- et al.
- 2007
- ISSCC 2007
Comparison of split- versus connected-core supplies in the POWER6™ microprocessor
- Norman James
- Phillip Restle
- et al.
- 2007
- ISSCC 2007
A 1V 18GHz clock generator in a 65nm PD-SOI technology
- Fadi H. Gebara
- Jeremy D. Schaub
- et al.
- 2007
- ISSCC 2007