Publications

16 results for E. Maciejewski

0.026μm² high performance Embedded DRAM in 22nm technology for server and SOC applications
- - C. Pei
  - G. Wang
  - et al.
- 2014
- IEDM 2014
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Deposited ALD SiO₂ high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- - S. Siddiqui
  - M.M. Chowdhury
  - et al.
- 2013
- ECS Meeting 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- - S. Narasimha
  - P. Chang
  - et al.
- 2012
- IEDM 2012
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- - Sungjae Lee
  - J. Johnson
  - et al.
- 2012
- VLSI Technology 2012
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
On the systematic analysis of ring-delay performance using statistical behavior model
- - Q. Liang
  - B. Greene
  - et al.
- 2009
- ISDRS 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- - M. Cai
  - B. Greene
  - et al.
- 2008
- IEEE International SOI Conference 2008
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- - S. Fang
  - S.S. Tan
  - et al.
- 2008
- ICSICT 2008