J.K. Gimzewski, T.A. Jung, et al.
Surface Science
A cost effective 28 nm CMOS Interconnect technology is presented for 28 nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated. © 2011 Elsevier B.V. All rights reserved.
J.K. Gimzewski, T.A. Jung, et al.
Surface Science
Sang-Min Park, Mark P. Stoykovich, et al.
Advanced Materials
Robert W. Keyes
Physical Review B
Mitsuru Ueda, Hideharu Mori, et al.
Journal of Polymer Science Part A: Polymer Chemistry