Study of channel length scaling in large-scale graphene FETs
Shu-Jen Han, Yanning Sun, et al.
VLSI Technology 2010
We demonstrate self-aligned fully-depleted 20-nm-thick In0.53Ga0.47As-channel MOSFETs using CMOS-compatible device structures and manufacturable process flows. These devices consist of self-aligned source/drain extensions and self-aligned raised source/drain with low sheet resistance of 360 and (115Ω) respectively. We demonstrate short-channel MOSFETs with gate lengths (LG) down to 30 nm, low series resistance (REXT=375 Ω μ m, and high peak saturation transconductance GMSAT=1275 μ) S(μ) m at (LG=50) nm and drain bias (VDS=0.5) V. We obtain long-channel capacitive inversion thickness TINV= 2.3) nm and effective mobility μ EFF=650) cm 2Big Vs at sheet carrier density (NS= 5 \times 1012) cm -2). Finally, using a calibrated quasi-ballistic FET model, we argue that for (LG≤ 20) nm, μEFF1000 cm2)/Vs will lead to short-channel MOSFETs operating within 10% of the ballistic limit. Thus, our III-V processes and device structures are well-suited for future generations of high-performance CMOS applications at short gate lengths and tight gate pitches.
Shu-Jen Han, Yanning Sun, et al.
VLSI Technology 2010
Jeehwan Kim, Can Bayram, et al.
Nature Communications
Can Bayram, Jeehwan Kim, et al.
SPIE OPTO 2015
Nicolas Daix, Emanuele Uccelli, et al.
APL Materials