J.-M. Halbout, P.G. May, et al.
TMPEO 1986
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
J.-M. Halbout, P.G. May, et al.
TMPEO 1986
Tze-Chiang Chen
VLSI Technology 2009
Tze-Chiang Chen
VLSI-TSA 2010
Keunwoo Kim, Hussein I. Hanafi, et al.
IEEE Transactions on Electron Devices