Mori Ohara 
contact information
Deputy Director of IBM Research - Tokyo, Distinguished Engineer, Chief Software Engineer for Hybrid Cloud on IBM hardware, Member of IBM Academy of TechnologyIBM Research - Tokyo, Japan +81
338085282
338085282 links
Professional Associations
Professional Associations: ACM | IEEE Computer Societymore information
More information: High Performance Commercial Systems2018
Aggregating requests among microservices
Nakaike Takuya, Ohara Moriyoshi
wait time, response time, network layer, microservices, micro services, computer science, computer network, application programming interface
Abstract
Nakaike Takuya, Ohara Moriyoshi
wait time, response time, network layer, microservices, micro services, computer science, computer network, application programming interface
Abstract
2017
Profile-based per-device code optimization
Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
US Patent 9,612,810
Abstract
Kiyokuni Kawachiya, Kazuaki Ishizaki, Moriyoshi Ohara, Mikio Takeuchi
US Patent 9,612,810
Abstract
2016
Merging sorted data arrays based on vector minimum, maximum, and permute instructions
Inoue, Hiroshi and Ohara, Moriyoshi and Komatsu, Hideaki
US Patent 9,298,419
Abstract
Inoue, Hiroshi and Ohara, Moriyoshi and Komatsu, Hideaki
US Patent 9,298,419
Abstract
2013
Parallel Execution Mechanism and Operating Method Thereof
Christian Jacobi, Marcel Mitran, Moriyoshi Ohara
US Patent App. 14/061,775
Christian Jacobi, Marcel Mitran, Moriyoshi Ohara
US Patent App. 14/061,775
Method and apparatus for controlling cache using transaction flags
Moriyoshi Ohara
US Patent 8,484,423
Moriyoshi Ohara
US Patent 8,484,423
2012
SIMD merge-sort and duplicate removal operations for data arrays
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
US Patent 8,261,043
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
US Patent 8,261,043
Image Data Transmission Apparatus and Method for Image Display System
Sanehiro Furuichi, Kei Kawase, Takenori Kohda, Moriyoshi Ohara
US Patent App. 13/442,048
Sanehiro Furuichi, Kei Kawase, Takenori Kohda, Moriyoshi Ohara
US Patent App. 13/442,048
Reduced data transfer during processor context switching
Hiroshi Inoue, Moriyoshi Ohara, Takao Moriyama, Yukihiko Sohda, Hideaki Komatsu
US Patent 8,266,627
Hiroshi Inoue, Moriyoshi Ohara, Takao Moriyama, Yukihiko Sohda, Hideaki Komatsu
US Patent 8,266,627
Converter, server system, conversion method and program
Hideaki Komatsu, Moriyoshi Ohara
US Patent 8,150,852
Hideaki Komatsu, Moriyoshi Ohara
US Patent 8,150,852
2009
Merge operations of data arrays based on SIMD instructions
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
US Patent 7,536,532
Hiroshi Inoue, Moriyoshi Ohara, Hideaki Komatsu
US Patent 7,536,532
Preprocessor to improve the performance of message-passing-based parallel programs on virtualized multi-core processors
Hiroshi Inoue, Hideaki Komatsu, Takao Moriyama, Moriyoshi Ohara, Yukihiko Sohda
US Patent 7,503,039
Hiroshi Inoue, Hideaki Komatsu, Takao Moriyama, Moriyoshi Ohara, Yukihiko Sohda
US Patent 7,503,039
2008
Fast implementation of decoding function for variable length encoding
Hiroshi Inoue, Hideaki Komatsu, Moriyoshi Ohara
US Patent 7,394,411
Hiroshi Inoue, Hideaki Komatsu, Moriyoshi Ohara
US Patent 7,394,411
Digital document browsing system and method thereof
Takenori Kohda, Katashi Nagao, Moriyoshi Ohara
US Patent 7,454,698
Takenori Kohda, Katashi Nagao, Moriyoshi Ohara
US Patent 7,454,698
2006
2004
Resource reservation system and resource reservation method and recording medium storing program for executing the method
Inoue, Hiroshi and Moriyama, Takao and Negishi, Yasushi and Ohara, Moriyoshi
US Patent App. 10/998,237
Abstract
Inoue, Hiroshi and Moriyama, Takao and Negishi, Yasushi and Ohara, Moriyoshi
US Patent App. 10/998,237
Abstract
2002
1993
Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity
Shimizu, Shigenori and Ohara, Moriyoshi
US Patent 5,228,136
Abstract
Shimizu, Shigenori and Ohara, Moriyoshi
US Patent 5,228,136
Abstract
Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity
Moriyoshi Ohara, Shigenori Shimizu
US Patent 5,228,136
Moriyoshi Ohara, Shigenori Shimizu
US Patent 5,228,136
Method and apparatus to maintain cache coherency in a multiprocessor system with each processor's private cache updating or invalidating its contents based upon set activity
Shimizu, Shigenori and Ohara, Moriyoshi
US Patent 5,228,136
Abstract
Shimizu, Shigenori and Ohara, Moriyoshi
US Patent 5,228,136
Abstract