Transfer Learning on Edge Using 14nm CMOS-compatible ReRAM Array and Analog In-memory Training Algorithm
- Takashi Ando
- Omobayode Fagbohungbe
- et al.
- 2025
- IEDM 2025
Publications
4 results for Paul Jamison
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
Reversing a decades-long scaling law of dielectric breakdown for ReRAM forming voltage reduction - Modeling competition among defect generation and annihilation processes
- Ernest Y Wu
- Takashi Ando
- et al.
- 2023
- IEDM 2023