An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011
Publications
101 results for Herschel Ainspan
A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO
- A. Goel
- Alexander V. Rylyakov
- et al.
- 2010
- VLSI Circuits 2010
Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009
A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS
- A. Rylyakov
- J. Tierno
- et al.
- 2008
- ISSCC 2008
Experimental analysis of substrate noise effect on PLL performance
- Woogeun Rhee
- Keith A. Jenkins
- et al.
- 2008
- IEEE TCAS-II
A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2007
- A-SSCC 2007
An ultra-compact differentially tuned 6-GHz CMOS LC-VCO with dynamic common-mode feedback
- Babak Soltanian
- Herschel Ainspan
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
Characteristics of submicron MOS varactors
- Keith A. Jenkins
- Herschel Ainspan
- 2006
- SiRF 2006