High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Publications
6 results for P. O'Neil
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Application of an SOI 0.12-μm CMOS technology to SoCs with low-power and high-frequency circuits
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2003
- IBM J. Res. Dev
Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
- K.W. Guarini
- A. Topol
- et al.
- 2002
- IEDM 2002
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
Suitability of scaled SOI CMOS for high-frequency analog circuits
- N. Zamdmer
- J.O. Plouchart
- et al.
- 2002
- ESSDERC 2002