Indranil R. Bardhan, Sugato Bagchi, et al.
JMIS
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Indranil R. Bardhan, Sugato Bagchi, et al.
JMIS
Michael D. Moffitt
ICCAD 2009
M.J. Slattery, Joan L. Mitchell
IBM J. Res. Dev
Ruixiong Tian, Zhe Xiang, et al.
Qinghua Daxue Xuebao/Journal of Tsinghua University