The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference Accelerator

This is a case study of how NorthPole, a neural inference accelerator with a highly novel architecture, was designed, verified, and fabricated successfully in first-silicon using a horizontally integrated design workflow centered on a cycle-accurate functional simulator called the NorthPole Validator. The Validator is NorthPole’s digital twin. The study demonstrates how the Validator’s scalable network-of-queues structure, consisting of approximately 26,000 nodes and 415,000 queues, let it easily pivot from architecture validation and compiler codesign, to logic and physical design verification, post-silicon testing, and software ecosystem development.