A direct-conversion receiver IC for WCDMA mobile systems
Scott K. Reynolds, Brian A. Floyd, et al.
IEEE Journal of Solid-State Circuits
A generalized architecture and theory for realizing multimodulus, sub-integer frequency division is developed by extending the phase-switched divider technique. The sub-integer divider consists of a pre-scaler, a phase rotator, a post-scaler, and a modulus controller. Phase rotation is proposed as an effective technique to realize fine phase resolution and thereby low sub-integer division ratios, as well as to eliminate the glitch which has plagued phase-switched dividers. Program-swallowed counters are used as the modulus controller to realize a broad-range multimodulus divider. Expressions are derived for the range and resolution of such a program-swallowed, phase-rotating divider. Furthermore, the fractional spurs from this divider topology are derived and related to the linearity of the phase rotator. It is shown that very low (-60 to -75 dBc) fractional spurs at the output of the divider can be attained with reasonably accurate phase rotators. The benefit of this technique is in the ability to realize sub-integer frequency synthesizers which have the architectural simplicity of standard integer-N PLLs, but the finer frequency resolution capabilities due to sub-integer division. © 2008 IEEE.
Scott K. Reynolds, Brian A. Floyd, et al.
IEEE Journal of Solid-State Circuits
Ullrich R. Pfeiffer, Scott K. Reynolds, et al.
RFIC 2004
Dong Gun Kam, Duixian Liu, et al.
IEEE Transactions on CPMT
Brian A. Floyd, Leathen Shi, et al.
IEEE T-MTT