Rongjian Liang, Hua Xiang, et al.
IEEE TCADIS
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs.
Rongjian Liang, Hua Xiang, et al.
IEEE TCADIS
David A. Papa, Tao Luo, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
He Zhou, Sunil P. Khatri, et al.
DAC 2019
Zhuo Li, C.N. Sze, et al.
ASP-DAC 2005