Kenneth P. Rodbell, David F. Heidel, et al.
IEEE TNS
Paper
Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells
Abstract
Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled. © 2006 IEEE.
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