William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
This paper describes simulation results for the collector resistance of a vertical pnp for complementary bipolar LSI, which can be fabricated by adding a p-well formation to the npn process[1]. It is found that the performance fT and current driving capability of such pnp devices are limited by the collector resistance Rc. A simple method for extracting the lumped Rc from a device simulator is described. The simulations show that the collector charging time adds a significant amount to emitter-to-collector delay, and the quasi-saturation in the collector junction limits its current driving capability. These observations highlight the importance of collector design in high performance pnp. © 1989.
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
A. Krol, C.J. Sher, et al.
Surface Science
Daniel J. Coady, Amanda C. Engler, et al.
ACS Macro Letters
Elizabeth A. Sholler, Frederick M. Meyer, et al.
SPIE AeroSense 1997