Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Daniel Brand, Reinaldo A. Bergamaschi, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, et al.
IEEE Design and Test of Computers