Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Related
Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Reinaldo A. Bergamaschi, Raul Camposano, et al.
Integration, the VLSI Journal
Conference paper
State-based power analysis for systems-on-chip
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003