Olivier Maher, N. Harnack, et al.
DRC 2023
Analog In-Memory Computing (AIMC) crossbars often face size limitations that hinder the mapping of entire neural network layers onto a single AIMC Tile. To overcome this, layers are typically distributed across multiple tiles or within a tile by multiplexing different sets of weights at various time intervals. However, this generates partial sums that must be accumulated along the bit lines to produce the final output, underscoring the need for integrated accumulation capabilities within AIMC systems. In this work, we propose a Near In- Memory High-Precision Accumulation Unit (NIMA) with builtin internal tile and external tile accumulation functionality, positioned at the periphery of the AIMC crossbar. This unit leverages the affine correction capabilities of existing systems and ensures high precision during partial sum accumulation. We have physically implemented NIMA in a 14nm CMOS technology, providing comprehensive performance and area evaluations and comparison with the prior art.We investigate and compare different layer mappings and accumulation schemes supported by the proposed unit, evaluating both latency and Mean Absolute Error (MAE). We further assess the precision of the proposed unit on large layers of ResNet9 and ResNet32 for image classification on CIFAR10/CIFAR100 datasets.
Olivier Maher, N. Harnack, et al.
DRC 2023
Tommaso Stecconi, Roberto Guido, et al.
Advanced Electronic Materials
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025
Xiaofan Zhang, Haoming Lu, et al.
MLSys 2020