A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990
Thermal scanning probe lithography combines high-resolution patterning capabilities with the ability to read topography without causing resist exposure. As such, it is an ideal candidate for the implementation of markerless pattern overlay. This approach eliminates errors arising from marker degradation and inconsistencies in the positioning hardware used for reading and writing. Here, we outline our implementation and characterization of a markerless lithography process. We demonstrate theoretically and experimentally that alignment errors below 5 nm are possible for micron-sized features having an amplitude of just 4 nm. Further, we show that following proper calibration, a limiting overlay accuracy of 1.1 nm per axis is achievable.
A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990
B.K. Boguraev, Mary S. Neff
HICSS 2000
Reena Elangovan, Shubham Jain, et al.
ACM TODAES
Chidanand Apté, Fred Damerau, et al.
ACM Transactions on Information Systems (TOIS)