Sonia Cafieri, Jon Lee, et al.
Journal of Global Optimization
As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.
Sonia Cafieri, Jon Lee, et al.
Journal of Global Optimization
György E. Révész
Theoretical Computer Science
Matthias Kaiserswerth
IEEE/ACM Transactions on Networking
Sabine Deligne, Ellen Eide, et al.
INTERSPEECH - Eurospeech 2001