C. Harder, P. Buchmann, et al.
Electronics Letters
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
C. Harder, P. Buchmann, et al.
Electronics Letters
P. Buchmann, H. Kaufmann, et al.
SPIE International Technical Symposium/Europe 1985
T. Morf, M. Kossel, et al.
Electronics Letters
F.R. Gfeller, P. Buchmann, et al.
IEEE Photonics Technology Letters