Conference paper
EXPERIMENT IN SILICON COMPILATION.
Viktors Berstis, D. Brand, et al.
ISCAS 1984
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
Viktors Berstis, D. Brand, et al.
ISCAS 1984
Sandip Kundu
IEICE Transactions on Information and Systems
D. Brand
ISSRE 2000
A. Devgan, Sandip Kundu
ASP-DAC 1998