Chia-Yu Chen, Jungwook Choi, et al.
AAAI 2018
Various defects during fabrication have been shown in the literature to introduce delay faults in logic circuits. This paper analyzes the effects of these defects on the normal operation of logic circuits with the goal of developing an appropriate model for these faults. Single and multiple delay faults in this model are analyzed to determine if they are redundant with respect to the normal operation of the logic circuit. The relationships between delay redundancies and stuck-at redundancies are discussed. The redundancy identification techniques are applied to various benchmarks circuits and experimental data are presented. © 1994 IEEE
Chia-Yu Chen, Jungwook Choi, et al.
AAAI 2018
M. Cho, Daniel Brand
ICML 2017
Vijay S. Iyengar
KDD 2002
Vijay S. Iyengar, Barry K. Rosen, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems