F.R. Gfeller, W. Hirt
International Zurich Seminar on Broadband Communications 2000
A 10:1 serializer/deserializer subsystem with fast byte synchronisation and link control functions has been designed. The subsystem, consisting of 1030 gates, was implemented on GaAs using a refractory-gate MESFET process and is part of an optoelectronic transmitter/receiver chip set for fibre-optic computer communication links. An operating speed of 1 Gbit/s was achieved with a power dissipation of only 1.2 W.
F.R. Gfeller, W. Hirt
International Zurich Seminar on Broadband Communications 2000
F.R. Gfeller, P. Buchmann, et al.
IEEE Photonics Technology Letters
F.R. Gfeller
Journal of Physics D: Applied Physics
M.B. Ritter, F.R. Gfeller, et al.
ISSCC 1996