Chihiro Kamidaki, Yuma Okuyama, et al.
IEICE Transactions on Electronics
94-GHz dual-polarized phased array transmitter and receiver ICs in 130 nm BiCMOS technology are reported. The transmitter IC integrates 16 transmitter front ends with two independent outputs, a 1-to-16 power splitter, and an intermediate frequency (IF)-to-RF up-converter. The receiver IC integrates 32 front ends, two separate 16-to-1 power combiners, and two RF-to-IF down-converters, which can either support a 32-element phased array or a 16-element polarimetric phased array if connected to 16 dual-polarized antennas. Both transmitter and receiver ICs include IF/baseband circuitry, a frequency synthesizer with continuous lock detection, a temperature sensor, and digital circuitry, including serial interface and front-end memory. On-wafer TX measurements at 94 GHz taken at 25 °C show an IF-to-RF conversion gain of 35 dB, oP1dB of 4 dBm, PSAT of 7.8 dBm per channel with a total power consumption of 3 W. On-wafer RX measurements at 94 GHz and 25 °C show a maximum RF-to-IF array conversion gain of 40 dB and an noise figure (NF) of 6 dB. The total RX power consumption varies from 3 to 4.6 W as it is configured from its minimum to its maximum RF front-end gain settings. RF phase shifting elements used in both TX and RX demonstrate a 1.6° phase resolution with 360° tuning range and gain variation (rms) lower than 0.5 dB. Phase-invariant gain tunability in TX and RX front ends has been achieved for independent tapering and beam steering, demonstrating the measured phase variation within ±0.5° for 10-dB gain tuning. Both TX and RX ICs are functional up to 105 °C, maintaining PSAT>6.5 dBm per channel in TX and NF < 12 dB in RX. The TX and RX ICs each have a chip size of 6.7 mm × 5.6 mm.
Chihiro Kamidaki, Yuma Okuyama, et al.
IEICE Transactions on Electronics
Chihiro Kamidaki, Yuma Okuyama, et al.
APMC 2022
Daeik Kim, Jonghae Kim, et al.
VLSI Circuits 2007
Gokce Keskin, Jonathan Proesel, et al.
IEEE Journal of Solid-State Circuits