Rajiv Ramaswami, Kumar N. Sivarajan
IEEE/ACM Transactions on Networking
Several illustrations of a general technique called the Algorithm and Architecture approach was presented. The programmer controlled unrolling of loops was demonstrated equivalent to customized vectorization of RISC-type code. Its use was illustrated to show that RS/6000 processors could compute the distribution (-1, 1) at the rate of 3.25 multiply-adds. A linear congruential generators, related to the multiplicative congruential generators was also specified.
Rajiv Ramaswami, Kumar N. Sivarajan
IEEE/ACM Transactions on Networking
Elena Cabrio, Philipp Cimiano, et al.
CLEF 2013
Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005