Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency without excessive computation times. Copyright © 1973 by The Institute of Electrical and Electronics Engineers, Inc.
Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
J.H. Kaufman, Owen R. Melroy, et al.
Synthetic Metals
Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
T.N. Morgan
Semiconductor Science and Technology