Samarth Agarwal, Jeffrey B. Johnson, et al.
Journal of Computational Electronics
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Samarth Agarwal, Jeffrey B. Johnson, et al.
Journal of Computational Electronics
Ning Lu
NSTI-Nanotech 2007
Ning Lu
ISQED 2008
Ning Lu, Pooja M. Kotecha, et al.
CICC 2014