S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005
As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed. © Copyright 2008 by International Business Machines Corporation.
S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005
Lixi Zhou, Jiaqing Chen, et al.
VLDB
György E. Révész
Theoretical Computer Science
A. Gupta, R. Gross, et al.
SPIE Advances in Semiconductors and Superconductors 1990