A high suppression frequency tripler for 60-GHz transceivers
Nadav Mazor, Oded Katz, et al.
IMS 2015
Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in diverse computing domains, directly and indirectly leading to diminishing performance returns as the many-core era is approaching. Novel interconnect technologies could help revert this trend by offering, among others, improved broadcast support, even in large-scale chip multiprocessors. This article outlines the prospects of wireless on-chip communication technologies pointing toward low-latency (a few cycles) and energy-efficient broadcast (a few picojoules per bit). It also discusses the challenges and potential impact of adopting these technologies as key enablers of unconventional hardware architectures and algorithmic approaches, in the pathway of significantly improving the performance, energy efficiency, scalability, and programmability of many-core chips.
Nadav Mazor, Oded Katz, et al.
IMS 2015
Mihai Sanduleanu, Alberto Valdes-Garcia, et al.
CICC 2013
Run Levinger, Benny Sheinman, et al.
IMS 2014
Nadav Mazor, Benny Sheinman, et al.
IEEE MWCL