Characteristics of submicron MOS varactors
Keith A. Jenkins, Herschel Ainspan
SiRF 2006
This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 μm CMOS technologies show good accuracy (error ∼5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 μm bulk CMOS technology and measured to demonstrate the operation of the test structure. © 2008 IEEE.
Keith A. Jenkins, Herschel Ainspan
SiRF 2006
Yanqing Wu, Yu-Ming Lin, et al.
IEDM 2010
Jae-Joon Kim, Barry P. Linder, et al.
IRPS 2011
Keith A. Jenkins
IEEE Design and Test of Computers