Record high RF performance for epitaxial graphene transistors
Yanqing Wu, Damon Farmer, et al.
IEDM 2011
Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-μm technology employs only 0.3 mm 2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip. © 2006 IEEE.
Yanqing Wu, Damon Farmer, et al.
IEDM 2011
Jean-Olivier Plouchart, Benjamin Parker, et al.
IEEE Design and Test
Yu-Ming Lin, Keith Jenkins, et al.
IEDM 2009
Alberto Valdes-Garcia, Arun Natarajan, et al.
RFIC 2013