Bodhisatwa Sadhu, Arun Paidimarri, et al.
IMS 2018
A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2-3.3 V and regulates the output from 0.7-0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of 2× 10-6. With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input.
Bodhisatwa Sadhu, Arun Paidimarri, et al.
IMS 2018
Caglar Ozdag, Arun Paidimarri, et al.
RFIC 2024
Arun Paidimarri, Masayuki Yoshiyama, et al.
RFIC 2021
Xiaoxiong Gu, Duixian Liu, et al.
IEEE MWCL