George A. Sai-Halasz, Matthew R. Wordeman, et al.
IEEE Electron Device Letters
Conference paper
A shorted global clock design for multi-GHz 3D stacked chips
Abstract
A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based technique. Both permit at-speed testing of the strata before and after stack assembly. The shorting-based technique is implemented in a 2-strata eDRAM test chip using an IBM 45nm SOI 3D technology. Operation above 2.5GHz is measured. © 2012 IEEE.
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