Aakrati Jain, Kamal Sikka, et al.
ECTC 2021
The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling.
Aakrati Jain, Kamal Sikka, et al.
ECTC 2021
Ruqiang Bao, K. Watanabe, et al.
VLSI Technology 2020
Son Nguyen, Thomas Haigh, et al.
MRS Fall Meeting 2022
Daniil Frolov
IMS 2025