Corey Liam Lammie, Hadjer Benmeziane, et al.
Nat. Rev. Electr. Eng.
A new Ge-GST embedded PCM cell architecture, optimized for Deep Neural Network (DNN) acceleration, is presented. Its integration flow is discussed, and its dimensions are optimized through TCAD simulations. Extensive electrical characterization of conductance levels is performed to assess analog programming and level stability over time and temperature. Simulations of large DNN demonstrate superior performance of the optimized cell when compared with standard Wall structure ePCM. Finally, functionality on a large statistic is demonstrated with the validation of a test-vehicle showing good process yield. Silicon implementation of a NN proves the excellent A-IMC characteristics of this architecture.
Corey Liam Lammie, Hadjer Benmeziane, et al.
Nat. Rev. Electr. Eng.
Olivier Maher, N. Harnack, et al.
DRC 2023
Tommaso Stecconi, Roberto Guido, et al.
Advanced Electronic Materials
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025