Design Limits of In-Memory Computing: Beyond the Crossbar
Gokul Krishnan, Jubin Hazra, et al.
EDTM 2021
A newly developed damascene structure to form high-density interconnect wiring is presented. The structure results in improved o‘en and short yields, lower sheet resistances, comparable contact/ via resistances, and shows excellent filling of high-aspect-ratio long lines with high copper content compared to currently used wiring fabricated by reactively ion etching (RIE) of Ti/ Al-Cu/ Ti/ TiN. The key leverage of this technique is the ability to combine soft and low resistance metal (A1 alloy, Cu alloy, etc.) deposited by physical vapor deposition (PVD) and a hard metal (W) deposited by chemical vapor deposition (CVD) with high wear resistance. As a result a structure with a good polish stop and better alloying capability, and high yields, while maintaining planarity at all levels can be fabricated. This structure is applied to a dense 512K SRAM (2-ns cycle/ 3.8-ns access time) design with 0.5-µm minimum ground rules resulting in improved yield of partially functional chips at second-level metal compared to the conventional RIE structure. © 1993 IEEE
Gokul Krishnan, Jubin Hazra, et al.
EDTM 2021
Rajiv V. Joshi, Matt Ziegler, et al.
CICC 2018
Rajiv V. Joshi, Matt Ziegler, et al.
IEEE JSSC
Wei Hwang, Rajiv V. Joshi, et al.
IEEE Journal of Solid-State Circuits