Conference paper
Generalized hierarchical all-to-all exchange patterns
Bogdan Prisacari, German Rodriguez, et al.
IPDPS 2013
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
Bogdan Prisacari, German Rodriguez, et al.
IPDPS 2013
Cyriel Minkenberg, Ronald P. Luijten, et al.
Computer Communication Review
Nikolaos Chrysos, Fredy Neeser, et al.
INA-OCMC 2014
Bogdan Prisacari, German Rodriguez, et al.
ICS 2013