Very low voltage (VLV) design
Ramon Bertran, Pradip Bose, et al.
ICCD 2017
This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with -0.63/0.67 LSB integral nonlinearity (INL) and -0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.
Ramon Bertran, Pradip Bose, et al.
ICCD 2017
John F. Bulzacchelli, Timothy O. Dickson, et al.
ISSCC 2009
Nandhini Chandramoorthy, Karthik Swaminathan, et al.
HPCA 2019
Hayun Chung, Alexander Rylyakov, et al.
VLSI Circuits 2009