A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
Pier Andrea Francese, Matthias Braendli, et al.
ISSCC 2016
A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and -5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate <10-12) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125-μm multimode fiber. The measured sensitivities at 56 and 32 Gb/s are -9- and -13-dBm optical modulation amplitude, respectively.
Pier Andrea Francese, Matthias Braendli, et al.
ISSCC 2016
Lukas Kull, Danny Luu, et al.
ISSCC 2018
Lukas Kull, Danny Luu, et al.
CSICS 2016
Alessandro Cevrero, Cosimo Aprile, et al.
VLSI Circuits 2015