Lukas Kull, Thomas Toifl, et al.
ISSCC 2013
A 24-72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist. High SNDR at Nyquist is achieved by 16 parallel sampling switches driven by short clock pulses. Clock-pulse edges can be shifted digitally to reduce the impact of timing mismatch. A total of 64 asynchronous 8-b successive approximation (SAR) ADCs at low supply voltage convert sampled voltages. The SAR ADCs use a differential capacitive DAC, one comparator per decision, and include a reference voltage DAC and buffer. The ADC consumes 2.0 pJ/conversion at 48 GS/s and 3.3 pJ/conversion at 72 GS/s and is implemented in 14-nm CMOS FinFET on 0.15 mm2.
Lukas Kull, Thomas Toifl, et al.
ISSCC 2013
Gain Kim, Marcel Kossel, et al.
IEEE JSSC
Lukas Kull, Danny Luu
CICC 2017
Marcel Kossel, Thomas Toifl, et al.
IEEE JSSC