Geoffrey Burr, Pritish Narayanan, et al.
VLSI Technology 2023
A 220-mm2, 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single-ended read-write-drive bus reduce the ICC4 current to ∼90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ∼1400 faults/chip with only 8% chip overhead.
Geoffrey Burr, Pritish Narayanan, et al.
VLSI Technology 2023
John Barth, William Reohr, et al.
ISSCC 2007
Brian L. Ji, Seiji Munetoh, et al.
VLSI Circuits 2003
Nauman Z. Butt, Kevin McStay, et al.
IEDM 2010