A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
Christian Menoifi, Matthias Braendli, et al.
ISSCC 2018
We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) < 10 -12 at a maximum frequency deviation of 350 ppm and a 2 7 -1 PRBS pattern. We propose a bit-sliced architecture for the data path, and a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. We present a novel method to characterize sampling latches and include them in the data path. A current-mode logic (CML) biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. The measured current consumption is 207 mA from a 1.1-V supply, and the active chip area is 0.12 mm 2. © 2006 IEEE.
Christian Menoifi, Matthias Braendli, et al.
ISSCC 2018
Christian Menolfi, Thomas Toifl, et al.
ISSCC 2011
Thomas Morf, Marc Seifried, et al.
Electronics Letters
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2018