Alessandro Cevrero, Ilter Ozkaya, et al.
VLSI Circuits 2017
A single-channel 12-bit SAR ADC achieving 250-340 MS/s and consuming 4.8-8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak SNDR and reaches 60.5-dB SNDR and 78.7-dB SFDR with 0.8-Vpp, diff input amplitude at Nyquist. It consumes 7.0 mW from a single 0.85-V supply, where 3.7 mW is contributed by the reference buffer. The key element is a comparator with an inverter-based preamplifier to achieve low-noise performance with below 1-Vpp, diff input amplitude. The common-mode (CM) sensitivity of the inverter is counteracted by an SAR-based CM regulation (CMREG). The regulation adjusts the sampled CM to the optimal CM for the maximum inverter gain using a second capacitive DAC. It adjusts the CM on a sample-by-sample basis and, thus, can correct time-varying CM. The implemented CMREG maintains SNDR above 60 dB for a differential input amplitude mismatch of up to 2 dB or a phase mismatch of up to 15°.
Alessandro Cevrero, Ilter Ozkaya, et al.
VLSI Circuits 2017
John F. Bulzacchelli, Christian Menolfi, et al.
IEEE JSSC
Lukas Kull, Danny Luu, et al.
CSICS 2016
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2018