Conference paper
3-D thermal modeling of FinFET
R.V. Joshi, José A. Pascual-Gutiérrez, et al.
ESSDERC 2005
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
R.V. Joshi, José A. Pascual-Gutiérrez, et al.
ESSDERC 2005
B.T. Jonker, H. Abad, et al.
Journal of Crystal Growth
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004
C.T. Chuang, Ken Chin
Bipolar Circuits and Technology Meeting 1990