P.F. Lu, C.T. Chuang
IEEE T-ED
An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0-8 /an double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9ps/2.2mW, 20.7ps/1.2mW, and 24.5ps/0.77mW have been achieved. © 1992, The Institution of Electrical Engineers. All rights reserved.
P.F. Lu, C.T. Chuang
IEEE T-ED
A. Petrou, J. Warnock, et al.
Solid State Communications
R.V. Joshi, C.T. Chuang, et al.
VLSI Technology 2001
B.S. Wu, C.T. Chuang, et al.
CICC 1992