Project Name

Main Memory Power, Performance, and Reliability Research


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IBM Research collaborates closely with IBM Server Development to enhance the performance, reliability, and energy-efficiency of IBM's server main memory systems. Concepts and technologies developed at IBM Research have been implemented in numerous generations of IBM System/x, System/p, and System/z servers. Recent publications in the DRAM main memory area include:

Publications

2010

The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies. J Stuecheli, D Kaseridis, D Daly, H C Hunter, L K John, Proceedings of the The ACM IEEE International Symposium on Computer Architecture (ISCA2010)

2009

Memory Quicksand: Unexpected Factors in Main Memory Power Management. H. Hunter, Workshop on Energy-Efficient Design, ISCA Conference, 2009

Packing in Bits: Power, Thermal, Electrical, and Packaging Constraints in Modern Memory Systems. H. Hunter, Workshop on Emerging Memory Technologies, ISCA Conference, 2009

Memory system design and DDR3/DDR4 trends. H. Hunter, Invited Tutorial at European PRACE Supercomputing Consortium, 2009

Scalability challenges for future memory. H. Hunter, V. Srinivasan, K. Wright, Tutorial at ISCA-36, 2009

2008

The Next Solution. H. Hunter and M. Qureshi, Panel at the Workshop on Memory Systems Performance and Correctness, ASPLOS Conference, 2008

Changing factors in memory system design: An end-to-end look at emerging challenges. H. Hunter and K. Wright, Tutorial at MICRO-41, 2008

2007

A 8Gb/s/pin, 9.6ns Row-Cycle 288Mb SDRAM with an I/O Error Detection Capability. K. Kim et al, IEEE Journal of Solid-State Circuits, Jan. 2007, pp. 193-200