Amlan Majumdar  Amlan Majumdar photo       

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Research Staff Member
T. J. Watson Research Center, Yorktown Heights, NY, USA
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Professional Associations

Professional Associations:  IEEE


U.S. PATENTS

  1. S. Datta, M. Radosavljevic, B. Doyle, J. Kavalieros, J. Brask, A. Majumdar, and R. S. Chau, “Carbon nanotube energy well (CNEW) field effect transistor”, US 7170120, Jan. 30, 2007. CITATIONS: 38.
  2. M. Radosavljevic, A. Majumdar, B. S. Doyle, J. Kavalieros, M. L. Doczy, J. K. Brask, U. Shah, S. Datta, and R. S. Chau, “Block contact architectures for nanoscale channel transistors”, US 7279375, Oct. 9, 2007. CITATIONS: 28.
  3. M. Radosavljevic, A. Majumdar, S. Datta , J. Brask, B. Doyle, and R. Chau, “Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dot in its gate dielectric”, US 7342277, Mar. 11, 2008.
  4. A. Majumdar, J. K. Brask, M. Radosavljevic, S. Datta, B. S. Doyle, M. L. Doczy, J. Kavalieros, M. V. Metz, R. Chau, U. Shah, and J. Blackwell, “Forming field-effect transistors from conductors”, US 7390947, Jun. 24, 2008.
  5. S. Datta, M. Radosavljevic, B. Doyle, J. Kavalieros, J. Brask, A. Majumdar, and R. S. Chau, “Carbon nanotube energy well (CNEW) field effect transistor”, US 7427541, Sept. 23, 2008.
  6. B. S. Doyle, S. Datta, J. T. Kavalieros, and A. Majumdar, “Method for ion implanting for tri-gate devices”, US 7449373, Nov. 11, 2008. CITATIONS: 31.
  7. J. K. Brask, J. Kavalieros, U. Shah, S. Datta, A. Majumdar, R. S. Chau, and B. Doyle, “Methods for patterning a semiconductor film”, US 7547637, Jun. 16, 2009.
  8. J. Cai, W. Haensch, and A. Majumdar, “Partially depleted SOI field effect transistor having a metallized source side halo region”, US 7601569, Oct. 13, 2009.
  9. M. Radosavljevic, A. Majumdar, S. Datta , J. Brask, B. Doyle, and R. Chau, “Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dot in its gate dielectric”, US 7608883, Oct. 27, 2009.
  10. M. Radosavljevic, J. T. Kavalieros, A. Majumdar, and S. Datta, “Directing carbon nanotube growth”, US 7638169, Dec. 29, 2009.
  11. A. Majumdar, R. T. Mo, Z. Ren, and J. W. Sleight, “Metal-gated MOSFET devices having scaled gate stack thickness”, US 7648868, Jan. 19, 2010.
  12. E. A. Cartier, S. J. Koester, K. Maitra, A. Majumdar, and R. T. Mo, “Extremely thin silicon-on-insulator transistor with raised source/drain”, US 7652332, Jan. 26, 2010. CITATIONS: 15.
  13. B. Y. Jin, J. T. Kavalieros, S. Datta, A. Majumdar, and R. S. Chau, “Mechanism for forming a remote delta doping layer of a quantum well structure”, US 7713803, May 11, 2010.
  14. R. H. Dennard, D. R. Greenberg, A. Majumdar, L. Shi, and J. B. Yau, “Low cost fabrication of double BOX back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer”, US 7767546, Aug. 3, 2010.
  15. A. B. Chakravarti, J. R. Holt, J. J. Kempisty, S. H. Ku, W. H. Lee, A. Majumdar, R. M. Mitchell, R. T. Mo, Z. Ren, and D. Singh, “Method for improving semiconductor surfaces”, US 7776624, Aug. 17, 2010.
  16. W. Haensch, S. J. Koester, and A. Majumdar, “Semiconductor structure including gate electrode having laterally variable work function”, US 7781288, Aug. 24, 2010.
  17. J. K. Brask, R. S. Chau, S. Datta, M. L. Doczy, B. S. Doyle, J. Kavalieros, A. Majumdar, M. V. Metz, and M. Radosavljevic, “Method for fabricating transistor with thinned channel”, US 7858481, Dec. 28, 2010.
  18. E. A. Cartier, S. J. Koester, K. Maitra, A. Majumdar, and R. T. Mo, “Extremely thin silicon-on-insulator transistor with raised source/drain”, US 7871869, Jan. 18, 2011.
  19. M. Radosavljevic, S. Datta, B. S. Doyle, J. Kavalieros, J. K. Brask, M. L. Doczy, A. Majumdar, and R. S. Chau, “Field effect transistor with metal source/drain regions”, US 7879675, Feb. 1, 2011.
  20. M. Radosavljevic, A. Majumdar, B. S. Doyle, J. Kavalieros, M. L. Doczy, J. K. Brask, U. Shah, S. Datta, and R. S. Chau, “Block contact architectures for nanoscale channel transistors”, US 7898041, Mar. 1, 2011. CITATIONS: 22.
  21. M. Radosavljevic, A. Majumdar, S. Datta, J. Kavalieros, B. S. Doyle, J. K. Brask, and R. S. Chau, “Fabrication of channel wraparound gate structure for field-effect transistor”, US 7915167, Mar. 29, 2011.
  22. J. Cai, W. Haensch, and A. Majumdar, “Partially depleted SOI field effect transistor having a metallized source side halo region”, US 7919812, Apr. 5, 2011.
  23. J. Cai, J. Chang, L. Chang, B. L. Ji, S. J. Koester, and A. Majumdar, “Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors”, US 7985633, Jun. 26, 2011.
  24. W. Haensch, S. J. Koester, and A. Majumdar, “Semiconductor structure including gate electrode having laterally variable work function”, US 7989900, Aug. 2, 2011.
  25. A. Majumdar, R. T. Mo, Z. Ren, and J. W. Sleight, “Metal-gated MOSFET devices having scaled gate stack thickness”, US 7993995, Aug. 9, 2011.
  26. A. Majumdar, G. Pei, Z. Ren, D. V. Singh, and J. W. Sleight, “Ultra-thin SOI CMOS with raised epitaxial source/drain and embedded SiGe PFET extension”, US 8012820, Sept. 6, 2011.
  27. L. Chang, B. L. Ji, A. Kumar, A. Majumdar, K. Saenger, L. Shi, and J. B. Yau, “Back-gated fully depleted SOI transistor”, US 8030145, Oct. 4, 2011.
  28. J. K. Brask, J. Kavalieros, U. Shah, S. Datta, A. Majumdar, R. S. Chau, and B. Doyle, “Semiconductor device structures and methods of forming semiconductor structures”, US 8071983, Dec. 6, 2011.
  29. J. Chang, M. Guillorn, I. Lauer, and, A. Majumdar, “Replacement spacer for tunnel FETs”, US 8178400, May 15, 2012.
  30. S. Datta, M. K. Hudait, M. L. Doczy, J. T. Kavalieros, A. Majumdar, J. K. Brask, B. Y. Jin, M. V. Metz, and R. S. Chau, “Extreme high mobility CMOS logic”, US 8183556, May 22, 2012.
  31. R. H. Dennard, D. R. Greenberg, A. Majumdar, L. Shi, and J. B. Yau, “Low cost fabrication of double BOX back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer”, US 8227865, Jun. 24, 2012.
  32. I. Lauer, A. Majumdar, P. M. Solomon, and S. J. Koester, “Fabrication of a vertical heterojunction tunnel FET”, US 8258031, Sept. 4, 2012.
  33. B. Y. Jin, J. T. Kavalieros, S. Datta, A. Majumdar, and R. S. Chau, “Mechanism for forming a remote delta doping layer of a quantum well structure”, US 8264004, Sept. 11, 2012.
  34. J. Cai, A. Majumdar, T. Ning, and Z. Ren, “Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method”, US 8314463, Nov. 20, 2012. CITATIONS: 25.
  35. S. Bangsaruntip, I. Lauer, A. Majumdar, and J. W. Sleight, “Nanowire tunnel field effect transistors”, US 8324030, Dec. 4, 2012.
  36. S. Bangsaruntip, G. Cohen, A. Majumdar, and J. W. Sleight, “Nanowire circuits in matched devices”, US8324940, Dec. 4, 2012.
  37. J. Cai, A. Majumdar, T. Ning, and Z. Ren, “Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method”, US 8329564, Dec. 12, 2012.
  38. S. Bangsaruntip, I. Lauer, A. Majumdar, and J. W. Sleight, “TFET with nanowire source”, US8343815, Jan. 1, 2013.
  39. R. Muralidhar, J. Cai, A. Majumdar, and G. Shahidi, “Semiconductor device with high-K dielectric control terminal spacer structure”, US 8349684, Jan. 8, 2013.
  40. K. Cheng, B. Doris, B. S. Haran, A. Majumdar, and S. Mehta, “Method to form low series resistance transistor devices on silicon on insulator layer”, US 8440552, May 14, 2013.
  41. S. Bangsaruntip, G. Cohen, A. Majumdar, and J. W. Sleight, “Generation of multiple diameter nanowire field effect transistors”, US 8445337, May 21, 2013.
  42. S. Bangsaruntip, G. Cohen, A. Majumdar, and J. W. Sleight, “Nanowire circuits in matched devices”, US 8520430, Aug. 8, 2013.
  43. J. Chang, M. Guillorn, I. Lauer, and, A. Majumdar, “Replacement spacer for tunnel FETs”, US 8530932, Sept. 10, 2013.
  44. K. Cheng, B. Doris, B. S. Haran, P. Kulkarni, N. Loubet, A. Majumdar, and S. Schmitz, “Semiconductor structure having NFET extension last implants”, US 8546203, Oct. 1, 2013.
  45. K. Cheng, B. Doris, B. S. Haran, A. Majumdar, and S. Mehta, “Low series resistance transistor structure on silicon on insulator layer”, US 8551872, Oct. 8, 2013.
  46. S. Bangsaruntip, G. Cohen, A. Majumdar, and J. W. Sleight, “Nanowire field effect transistors”, US 8558219, Oct. 15, 2013.
  47. J. K. Brask, J. Kavalieros, U. Shah, S. Datta, A. Majumdar, R. S. Chau, and B. Doyle, “Semiconductor device structures and methods of forming semiconductor structures”, US 8581258, Nov. 12, 2013.
  48. A. Majumdar and X. Wang, “Stressed source/drain CMOS and method of forming same”, US 8603894, Dec. 10, 2013.
  49. S. Bangsaruntip, G. Cohen, A. Majumdar, and J. W. Sleight, “Nanowire field effect transistors”, US 8648330, Feb. 11, 2014.
  50. T. N. Adam, K. Cheng, B. B. Doris, B. S. Haran, P. Kulkarni, A. Majumdar, and S. Schmitz, “Semiconductor structure having NFET extension last implants”, US 8673699, Mar. 18, 2014.
  51. A. Majumdar, R. J. Miller, and M. Ramachandran, “Semiconductor device having localized extremely thin silicon on insulator channel region”, US 8685847, Apr. 1, 2014.
  52. S. Bangsaruntip, S. J. Koester, and A. Majumdar, and J. W. Sleight, “Nanowire PIN tunnel field effect device”, US 8,722,492, May 13, 2014.
  53. S. Bangsaruntip, I. Lauer, A. Majumdar, and J. W. Sleight, “Nanowire tunnel field effect transistors”, US 8,723,162, May 13, 2014.