Alper Buyuktosunoglu  Alper Buyuktosunoglu photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA

links

Professional Associations

Professional Associations:  ACM  |  Fellow, IEEE  |  IEEE   |  IEEE Computer Society


 

  1. Space Reduction in Processor Stressmark Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,804,849, issued 10/31/2017
  2. Space Reduction in Processor Stressmark Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,798,546, issued 10/24/2017
  3. Processor with Memory-Embedded Pipeline for Table-Driven Computation, P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,740,497, issued 08/22/2017
  4. Processor with Memory-Embedded Pipeline for Table-Driven Computation, P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,740,496, issued 08/22/2017
  5. Generation and Application of Stressmarks in a Computer System, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,727,434, issued 08/08/2017
  6. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A.Buyuktosunoglu, H. Franke, P. Tembey, D. Silva, number 9,710,044, issued 07/18/2017
  7. Three-Dimensional Processing System Having at Least One Layer with Circuitry Dedicated to Scan Testing and System State Checkpointing of Other System Layers, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,696,379, issued 07/04/2017
  8. Optimization of Application Workflow in Mobile Embedded Devices, R. Bertran, P. Bose, A. Buyuktosunoglu, C. Cher, H. Jacobson, W. Song, K. Swaminathan, A. Vega, L. Wang, number 9,690,555, issued 06/27/2017
  9. Predicting Out-of-Order Instruction Level Parallelism Of Threads in a Multi-Threaded Processor, I. Burcea, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,652,243, issued 05/16/2017
  10. Intelligent Bandwidth Shifting Mechanism, P. Bose, A. Buyuktosunoglu, V. Jimenez, F. O'Connell, number 9,645,935, issued 05/09/2017
  11. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,632,560, issued 04/25/2017
  12. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,632,559, issued 04/25/2017
  13. Single-Thread Cache Miss Rate Estimation, J. Bonanno, A. Buyuktosunoglu, B. Curran, W. Hinrichs, C. Jacobi, B. Prasky, M. Recktenwald, A. Saporito, V. Srinivasan, J. Wellman, number  9,626,293, issued 04/18/2017
  14. Single-Thread Cache Miss Rate Estimation, J. Bonanno, A. Buyuktosunoglu, B. Curran, W. Hinrichs, C. Jacobi, B. Prasky, M. Recktenwald, A. Saporito, V. Srinivasan, J. Wellman, number  9,619,385, issued 04/11/2017
  15. Idle-Aware Margin Adaption, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,618,999, issued 04/11/2017
  16. Generation and Application of Stressmarks in a Computer System, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,588,863, issued 03/07/2017
  17. Processor Stressmarks Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, number 9,575,868, issued 02/21/2017
  18. Processor Stressmarks Generation, R. Bertran, P. Bose, A. Buyuktosunoglu, number 9,575,867, issued 02/21/2017
  19. 3-D Stacked Multiprocessor Structure with Vertically Aligned Identical Layout Operating Processors in Independent Mode or in Sharing Mode Running Faster Components, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,569,402, issued 02/14/2017
  20. Cycle-Level Thread Alignment on Multi-Threaded Processors, R. Bertran, P. Bose, A. Buyuktosunoglu, T. Slegel, number 9,507,646, issued 11/29/2016
  21. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 2513787(UK), issued 11/23/2016 (also issued as ZL201380008222.1 on 10/05/2016)
  22. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,471,535, issued 10/18/2016 (also issued as ZL201310137022.8 on 12/28/2016)
  23. Predictively Turning Off a Charge Pump Supplying Voltage for Overdriving Gates of the Power Switch Header in a Microprocessor with Power Gating, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,471,136, issued 10/18/2016
  24. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,442,884, issued 09/13/2016
  25. Determining and Storing Bit Error Rate Relationships in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,431,084, issued 08/30/2016
  26. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,424,308, issued 08/23/2016
  27. Accelerating Microprocessor Core Wake Up via Charge from Capacitance Tank Without Introducing Noise on Power Grid of Running Microprocessor Cores, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,423,865, issued 08/23/2016
  28. Delaying Execution in a Processor to Increase Power Savings, P. Bose, A. Buyuktosunoglu, H. Jacobson, A. Vega, number 9,423,859, issued 08/23/2016
  29. Determining and Storing Bit Error Rate Relationships in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,418,721, issued 08/16/2016
  30. Dynamic Temperature Adjustments in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,406,368, issued 08/02/2016
  31. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,396,143, issued 07/19/2016
  32. Three-Dimensional Processing System Having Independent Calibration and Statistical Collection Layer, A. Buyuktosunoglu, P.Emma, A. Hartstein, M. Healy, K. Kailas, number 9,389,876, issued 07/12/2016
  33. Power Management for In-Memory Computer Systems, P. Bose, A. Buyuktosunoglu, B. Fleischer, T. Fox, H. Jacobson, R. Nair, A. Vega, number 9,389,675, issued 07/12/2016
  34. Predictively Turning Off a Charge Pump Supplying Voltage for Overdriving Gates of the Power Switch Header in a Microprocessor with Power Gating, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,389,674, issued 07/12/2016
  35. Three-Dimensional Processing System Having at Least One Layer with Circuitry Dedicated to Scan Testing and System State Checkpointing of Other System Layers, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,383,411, issued 07/05/2016
  36. Dynamic Power Distribution, P. Bose, A. Buyuktosunoglu, H. Jacobson, number 9,372,519, issued 06/21/2016
  37. Dynamic Detection of Resource Management Anomalies in a Processing System, P. Bose, A. Buyuktosunoglu, A. Vega, number 9,361,175, issued 06/07/2016
  38. Power Management for Multi-Core Processing Systems, P. Bose, A. Buyuktosunoglu, M. Floyd, H. Hanson, H. Jacobson, K. Rajamani, S. Ramani, T. Rosedahl, A. Vega, number 9,354,943, issued 05/31/2016
  39. Dynamic Temperature Adjustments in Spin Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM), P. Bose, A. Buyuktosunoglu, X. Guo, H. Hunter, J. Rivers, V. Srinivasan, number 9,351,899, issued 05/31/2016
  40. Three-Dimensional Processing System Having Multiple Caches That Can Be Partitioned, Conjoined, and Managed According to More Than One Set of Rules and/or Configurations, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,336,144, issued 05/10/2016
  41. Rotating Voltage Control, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,323,302, issued 04/26/2016
  42. 3-D Stacked Multiprocessor Structures and Methods for Multimodal Operation of Same, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number ZL201310137331.5, issued 03/30/2016
  43. Dynamic Power Distribution, P. Bose, A. Buyuktosunoglu, H. Jacobson, number 9,298,234, issued 03/29/2016
  44. Accelerating the Microprocessor Core Wakeup by Predictively Executing a Subset of the Power-Up Sequence, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,298,253, issued 03/29/2016
  45. 3-D Stacked Multiprocessor Structure with Vertically Aligned Identical Layout Operating Processors in Independent Mode or in Sharing Mode Running Faster Components, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,298,672, issued 03/29/2016
  46. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,298,466, issued 03/29/2016
  47. Accelerating the Microprocessor Core Wakeup by Predictively Executing a Subset of the Power-Up Sequence, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number 9,292,079, issued 03/22/2016
  48. Hierarchical In-Memory Sort Engine, A. Buyuktosunoglu, S. Chellappa, T. Kirihata, K. Swaminathan, number 9,268,863, issued 02/23/2016
  49. Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,257,152, issued 02/09/2016
  50. Three-Dimensional Computer Processor Systems Having Multiple Local Power and Cooling Layers and A Global Interconnection Structure, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, M. Scheuermann, number 9,195,630, issued 11/24/2015
  51. Memory Architectures Having Wiring Structures that Enable Different Access Patterns in Multiple Dimensions, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 9,190,118, issued 11/17/2015
  52. Multi-Threaded Processor Instruction Balancing Through Instruction Uncertainty, A. Buyuktosunoglu, B. Prasky, V. Srinivasan, number 9,182,991, issued 11/10/2015
  53. Thread Consolidation in Processor Cores, P. Bose, A. Buyuktosunoglu, B. Rosenburg, K. Ryu, A. Vega, number 9,146,609, issued 9/29/2015
  54. Thread Consolidation in Processor Cores, P. Bose, A. Buyuktosunoglu, B. Rosenburg, K. Ryu, A. Vega, number 9,141,173, issued 9/22/2015
  55. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A. Buyuktosunoglu, D. Silva, H. Franke, P. Tembey, number 9,043,626, issued 5/26/2015
  56. Power Shifting in Multicore Platforms by Varying SMT Levels, P. Bose, A. Buyuktosunoglu, D. Silva, H. Franke, P. Tembey, number 9,003,218, issued 4/7/2015
  57. Adaptive Workload Based Optimizations Coupled with a Heterogeneous Current-Aware Baseline Design to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,914,764, issued 12/16/2014
  58. Current-Aware Floorplanning to Overcome Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,863,068, issued 10/14/2014
  59. Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,826,216, issued 9/2/2014
  60. 3-D Stacked Multiprocessor Structures and Methods to Enable Reliable Operation of Processors at Speeds above Specified Limits, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 8,826,073, issued 9/2/2014
  61. 3-D Stacked Multiprocessor Structures and Methods to Enable Reliable Operation of Processors at Speeds above Specified Limits, A. Buyuktosunoglu, P. Emma, A. Hartstein, M. Healy, K. Kailas, number 8,799,710, issued 8/5/2014
  62. Virtualized Abstraction with Built-in Data Alignment and Simultaneous Event Monitoring in Performance Counter Based Application Characterization and Tuning, P. Bose, A. Buyuktosunoglu, C. Isci, J. Kephart, X. Meng, R. Sarikaya, number 8,798,962, issued 8/5/2014
  63. A Method and System for Computing a Single Thread Performance in a Simultaneous Multithreading Environment, J. Bartik, A. Buyuktosunoglu, B. Curran, C. Jacobi, B. Prasky, J. Wellman, V. Srinivasan, number IPCOM000237737D, published 7/8/2014
  64. An Apparatus for Regulating Voltage by Using Header Devices with Variable Gate Voltage, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number IPCOM000237598D, published 6/26/2014
  65. Apparatus to Provide Multiple Virtual Supply Voltage Points Through Selective Activation of Header Devices, P. Bose, A. Buyuktosunoglu, H. Jacobson, V. Zyuban, number IPCOM000237597D, published 6/26/2014
  66. Adaptive Workload Based Optimizations to Mitigate Current Delivery Limitations in Integrated Circuits, P. Bose, A. Buyuktosunoglu, J. Darringer, M. Qureshi, J. Shin, number 8,683,418, issued 3/25/2014
  67. On-Chip Power Proxy Based Architecture, P. Bose, A. Buyuktosunoglu, M. Floyd, M. Pesantez, number 8,650,413, issued 2/11/2014
  68. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 8,639,955, issued 1/28/2014
  69. Dynamically Tune Power Proxy Architectures, E. Acar, P. Bose, B. Brock, A. Buyuktosunoglu, M. Floyd, M. Pesantez, G. Still, number 8,635,483, issued 1/21/2014
  70. Voltage Regulator Module with Power Gating and Bypass, P. Bose, A. Buyuktosunoglu, H. Jacobson, S. Kim, number 8,564,262, issued 10/22/2013
  71. Guarded, Multi-Metric Resource Control for Safe and Efficient Microprocessor Management, P. Bose, A. Buyuktosunoglu, N. Madan, number 8,527,994, issued 9/3/2013
  72. Measuring Data Switching Activity in a Microprocessor, P. Bose, A. Buyuktosunoglu, C. Gonzalez, M. Qureshi, V. Zyuban, number 8,458,501, issued 6/4/2013
  73. Systems and Methods for Thread Assignment and Core Turn-Off for Integrated Circuit Energy Efficiency and High Performance, P. Bose, A. Buyuktosunoglu, E. Kursun, number 8,296,773, issued 10/23/2012
  74. On-Chip Power Proxy Based Architecture, P. Bose, A. Buyuktosunoglu, M. Floyd, number 8,271,809, issued 9/18/2012
  75. Managing Instructions for More Efficient Load/Store Unit Usage, P. Bose, A. Buyuktosunoglu, M. Floyd, D. Nguyen, B. Ronchetti, number 8,271,765, issued 9/18/2012
  76. Power Efficient Thread Priority Enablement, P. Bose, A. Buyuktosunoglu, R. Eickemeyer, S. Eisen, M. Floyd, H. Jacobson, J. Summers, number 8,261,276, issued 9/4/2012
  77. Predictive Power Gating with Optional Guard Mechanism, J. Basak, P. Bose, A. Buyuktosunoglu, A. Lungu, number 8,219,834, issued 7/10/2012
  78. Two-Level Guarded Predictive Power Gating, J. Basak, P. Bose, A. Buyuktosunoglu, A. Lungu, number 8,219,833, issued 7/10/2012
  79. System of Programmable Mode Control within an Instruction Sequencing Unit for Management of Power within a Microprocessor, P. Bose, A. Buyuktosunoglu, M. Floyd, T. Venton, V. Zyuban, number IPCOM000217762D, published 5/11/2012
  80. Adaptive Data Prefetch System and Method, P. Bose, A. Buyuktosunoglu, M. Dooley, M. Floyd, D. Ray, B. Ronchetti, number 8,156,287, issued 4/10/2012
  81. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 8,112,642, issued 2/7/2012
  82. Self-Tuning Power Management Techniques, R. Bergamaschi, A. Buyuktosunoglu, G. Dittmann, I. Nair, number 8,001,405, issued 8/16/2011
  83. Method and System of Multi-Core Microprocessor Power Management and Control via Per-Chiplet, Programmable Power Modes, P. Bose, A. Buyuktosunoglu, M. Floyd, number 8,001,394, issued 8/16/2011
  84. Method and System of Peak Power Enforcement via Autonomous Token-based Control and Management, P. Bose, A. Buyuktosunoglu, C. Cher, Z. Hu, H. Jacobson, P. Kudva, V. Srinivasan, V. Zyuban, number 7,930,578, issued 4/19/2011
  85. Integrated Co-optimized Adaptive On-chip Power Management Techniques for Multi-Core Systems, R. Bergamaschi, P. Bose, A. Buyuktosunoglu, J. Darringer, G. Dittmann, M. Floyd, I. Nair, number IPCOM000204964D, published 3/14/2011
  86. Dynamic Reconfigurable Memory Hierarchy, D. Albonesi, R. Balasubramonian, A. Buyuktosunoglu, S. Dwarkadas, number 6,684,298, issued 1/27/2004 (reissued as RE42,213 on 3/8/2011)
  87. Adaptive Issue Queue for Reduced Power at High Performance, A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, D. Albonesi, number 7,865,747, issued 1/4/2011
  88. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, D. Albonesi, R. Balasubramonian, A. Buyuktosunoglu, S. Dwarkadas, number 6,834,328, issued 12/21/2004 (reissued as RE41,958 on 11/23/2010)
  89. System and Method for Predicting Hardware and/or Software Metrics in a Computer System Using Models, A. Buyuktosunoglu, R. Sarikaya, number 7,698,249, issued 4/13/2010
  90. Method and Apparatus for Conserving Power by Throttling Instruction Fetching when a Processor Encounters Low Confidence Branches in an Information Handling System, P. Bose, A. Buyuktosunoglu, C. Cher, M. Gschwind, R. Nair, R. Philhower, W. Sauer, R. Yeung, number 7,627,742, issued 12/1/2009 (also issued as ZL200880011619.5 on 10/12/2011, also issued as 1159407 on 6/18/2012, also issued as 5172942 on 1/11/2013)
  91. Methods for Thermal Management of Three-Dimensional Integrated Circuits, P. Bose, A. Buyuktosunoglu, E. Kursun, number 7,487,012, issued 2/3/2009
  92. Cost-Conscious Pre-Emptive Cache Line Displacement and Relocation Mechanisms, A. Buyuktosunoglu, Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number 7,454,573, issued 11/18/2008
  93. Arrangements for Reducing Latency and Snooping Cost in Non-Uniform Cache Memory Architectures, A. Buyuktosunoglu, Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number CN ZL200610005935.4, issued 11/5/2008
  94. Systems and Methods for Mutually Exclusive Activation of Microprocessor Resources to Control Maximum Power, P. Bose, A. Buyuktosunoglu, Z. Hu, H. Jacobson, V. Srinivasan, V. Zyuban, number 7,447,923, issued 11/4/2008 (also issued as ZL200680030136.0 on 5/4/2011, as 4811879 on 9/2/2011)
  95. Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, P. Bose, A. Buyuktosunoglu, C. Cher, P. Kudva, number 7,421,601, issued 9/02/2008
  96. Adaptive Fetch Gating in Multithreaded Processors, Fetch Control and Method of Controlling Fetches, P. Bose, A. Buyuktosunoglu, R. Eickemeyer, L. Eisen, P. Emma, J. Griswell, Z. Hu, H. Le, D. Logan, B. Sinharoy, number 7,392,366, issued 6/24/2008
  97. Apparatus and Method for Dynamic Control of Double Gate Devices, A. Buyuktosunoglu, O. Dokumaci, number 7,170,772, issued 1/30/2007
  98. Method and Structure for Short Range Leakage Control in Pipelined Circuits, H. Jacobson, P. Bose, A. Buyuktosunoglu, P. Cook, P. Emma, P. Kudva, S. Schuster,number 6,946,869, issued 9/20/2005