John David Wellman  John David Wellman photo       

contact information

Research
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash2523

links



2008

Phaser: Phased methodology for modeling the system-level effects of soft errors
JA Rivers, P Bose, P Kudva, J D Wellman, PN Sanda, EH Cannon, LC Alves
IBM Journal of Research and Development 52(3), 293--306, IBM, 2008


2004

Exploring real time multimedia content creation in video games
B Matthews, J D Wellman, M Gschwind
6th Workshop on Media and Streaming Processors, 2004


2003

Reducing instruction fetch energy with backwards branch control information and buffering
J A Rivers, S Asaad, J D Wellman, J H Moreno
Proceedings of the 2003 international symposium on Low power electronics and design, pp. 322--325


2001

Power-performance modeling and tradeoff analysis for a high end microprocessor
D Brooks, M Martonosi, J D Wellman, P Bose
Power-Aware Computer Systems, 126--136, Springer, 2001


2000

Research Center." Power-Aware Microarchitecture: Modeling Challenges for Next-Generation Microprocessors
David M Brooks, Pradip Bose, Stanley E Schuster, Hans Jacobson, Prabhakar N Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, Peter W Cook IBM TJ Watson
IEEE Micro 20(6), 2000

Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
D M Brooks, P Bose, S E Schuster, H Jacobson, P N Kudva, A Buyuktosunoglu, J Wellman, V Zyuban, M Gupta, P W Cook
Micro, IEEE 20(6), 26--44, IEEE, 2000


1999

Environment for PowerPC microarchitecture exploration
M Moudgill, J D Wellman, J H Moreno
Micro, IEEE 19(3), 15--25, IEEE, 1999


1998

An approach for quantifying the impact of not simulating mispredicted paths
M Moudgill, J D Wellman, J H Moreno
Performance Analysis and Its Impact in Design, Citeseer, 1998


1997

PARSIM: A parallel trace-driven simulation facility for fast and accurate performance analysis studies
A-T Nguyen, John-David Wellman, Pradip Bose
Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International, pp. 291--297

Trace-driven performance exploration of a PowerPC 601 OLTP workload on wide superscalar processors
J H Moreno, M Moudgill, J D Wellman, P Bose, L Trevillyan
1997 - research.ibm.com, IBM TJ Watson Research Center


1996



1995

The resource conflict methodology for early-stage design space exploration of superscalar RISC processors
J D Wellman, E S Davidson
Computer Design: VLSI in Computers and Processors, 1995, pp. 110--115


1993

Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads
E L Boyd, J D Wellman, S G Abraham, E S Davidson
Proceedings of the 7th international conference on Supercomputing, pp. 240--250, 1993


Year Unknown

General Chair Tom Dillinger, IBM Corporation Technical Program Chair Ed Grochowski, Intel Corporation Past Chair
K Shepard, P M Seidel, D Grunwald, J D Wellman, P Dubey, W R Davis, S Dutt, S Dey
iccd.et.tudelft.nl, 0

Aria: an execution simulation environment for microarchitectural analyses
JD Wellman, M Moudgill
Research Report (in preparation), IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 0

The MET: A Microarchitecture Exploration Toolset
J Moreno, M Moudgill, JD Wellman, P Bose
Technical Report, Research Report (in preparation), IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 0

Turandot: A PowerPC-based wide-issue superscalar processor model for microarchitecture exploration
M Moudgill, J Moreno, P Bose, JD Wellman
Technical Report, Research Report (in preparation), IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 0