Vijayalakshmi (Viji) Srinivasan  Vijayalakshmi  (Viji) Srinivasan photo       

contact information

research
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  ACM SIGARCH  |  ACM SIGMICRO  |  CRA-W  |  IEEE


2013


Write-through cache optimized for dependence-free parallel regions
Alexandre E Eichenberger, Alan G Gara, Martin Ohmacht, Vijayalakshmi Srinivasan
US Patent 8,516,197

Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 8,521,999

Non-data inclusive coherent (nic) directory for cache
Timothy C Bronson, Garrett M Drapala, Rebecca M Gott, Pak-Kin Mak, Vijayalakshmi Srinivasan, Craig R Walters
US Patent App. 13/784,958


2012


Methods of cache preloading on a partition or a context switch
Harold W Cain III, Vijayalakshmi Srinivasan, Jason Zebchuk
US Patent App. 13/545,304

Structure for implementing dynamic refresh protocols for DRAM based cache
John E Barth, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,108,609


2011

Method and system for integrating SRAM and DRAM architecture in set associative cache
Marc R Faucher, Hillery C Hunter, William R Reohr, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 7,962,695

Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor
Ioana Monica Burcea, Alper Buyuktosunoglu, Brian Robert Prasky, Vijayalakshmi Srinivasan
US Patent App. 13/172,218




Relaxation of synchronization for iterative convergent computations
Lakshminarayanan Renganarayana, Vijayalakshmi Srinivasan
US Patent App. 13/184,718

Method and system for providing an improved store-in cache
Philip George Emma, Wing K Luk, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent 7,941,728

Method and system for implementing dynamic refresh protocols for DRAM based cache
John E Barth Jr, Philip G Emma, Erik L Hedberg, Hillery C Hunter, Peter A Sandon, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent 8,024,513

Iterative write pausing techniques to improve read latency of memory systems
Michele M Franceschini, Luis A Lastras-Montano, Moinuddin K Qureshi, Vijayalakshmi Srinivasan
US Patent 8,004,884




2010


Prefetching branch prediction mechanisms
Philip G Emma, Allan M Hartstein, Brian R Prasky, Thomas R Puzak, Vijayalakshmi Srinivasan
US Patent App. 12/721,933


2009

Processor Core Stacking for Efficient Collaboration
Philip G Emma, Eren Kursun, Moin K Qureshi, Viji Srinivasan
US Patent App. 12/570,351

Sectored cache memory
Philip G Emma, Robert K Montoye, Vijayalakshmi Srinivasan
US Patent 7,526,610

Method and apparatus for prefetching branch history information
Philip G Emma, Klaus J Getzlaff, Allan M Hartstein, Thomas Pflueger, Thomas R Puzak, Eric Mark Schwarz, Vijayalakshmi Srinivasan
US Patent 7,493,480



2008

Embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/019,818

Design structure for an embedded dram having multi-use refresh cycles
John E Barth Jr, Philip G Emma, Hillery C Hunter, Vijayalakshmi Srinivasan, Arnold S Tran
US Patent App. 12/103,290

Methods involving memory caches
Philip G Emma, Robert K Montoye, Vijayalakshmi Srinivasan
US Patent 7,472,226

Context look ahead storage structures
Philip George Emma, Allan Mark Hartstein, Brian R Prasky, Thomas Roberts Puzak, Moinuddin Khalil Ahmed Qureshi, Vijayalakshmi Srinivasan
US Patent 7,337,271

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power
Pradip Bose, Alper Buyuktosunoglu, Zhigang Hu, Hans Mikael Jacobson, Vijayalakshmi Srinivasan, Victor Zyuban
US Patent 7,447,923

COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,090/083,492



2006





2005

Handling permanent and transient errors using a SIMD unit
Erik Altman, Gheorghe Cascaval, Luis Ceze, Vijayalakshmi Srinivasan
US Patent App. 11/063,122

Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures
A Buyuktosunoglu, Z Hu, J A Rivers, J T Robinson, X Shen, V Srinivasan
US Patent App. 20,060/248,287


2003

Branch history guided instruction/data prefetching
Thomas R Puzak, Allan M Hartstein, Mark Charney, Daniel A Prener, Peter H Oden, Vijayalakshmi Srinivasan
US Patent 6,560,693


2002

Two dimensional branch history table prefetching mechanism
Philip Emma, Klaus Getzlaff, Allan Hartstein, Thomas Pflueger, Thomas Puzak, Eric Schwarz, Vijayalakshmi Srinivasan