Phillip J. Restle  Phillip J. Restle photo       

contact information

Distinguished-RSM: Clocking & Power-Noise Mitigation for IBM Systems
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IBM Academy of Technology  |  IEEE, Senior Member


2017

Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection
Michael S Floyd, Phillip J Restle, Michael A Sperling, Pawel Owczarczyk, Eric J Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis
IEEE ISSCC, 2017

Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection
Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard Rizzolo, Tobias Webel, Thomas Strach, Otto Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael Floyd, Malcolm Ware, Gerard Salem, Sean Carey, Phillip Restle
IEEE ISSCC Technical Digest, 2017


2015

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking
Fluhr, Eric J and Baumgartner, Steve and Boerstler, David and Bulzacchelli, John F and Diemoz, Timothy and Dreps, Daniel and English, George and Friedrich, Joshua and Gattiker, Anne and Gloekler, Tilman and others
IEEE Journal of Solid-State Circuits 50(1), 10--23, IEEE, 2015
Abstract

IBM POWER8 circuit design and energy optimization
Zyuban, V and Friedrich, Joshua and Dreps, Daniel M and Pille, J{\"u}rgen and Plass, Donald W and Restle, Phillip J and Deniz, Zeynep Toprak and Ziegler, Matthew M and Chu, S and Islam, S and others
IBM Journal of Research and Development 59(1), 9--1, IBM, 2015
Abstract

Resonant clock mega-mesh for the IBM z13 TM
Shan, David and Restle, Phillip and Malone, Doug and Groves, Rob and Lai, Eric and Koch, Michael and Hibbeler, Jason and Kim, Yong and Vezyrtzis, Christos and Feder, Jan and others
VLSI Circuits (VLSI Circuits), 2015 Symposium on, pp. C322--C323
Abstract


2014

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 TM microprocessor
Restle, Phillip and Shan, David and Hogenmiller, David and Kim, Yong and Drake, Alan and Hibbeler, Jason and Bucelot, Thomas and Still, Gregory and Jenkins, Keith and Friedrich, Joshua
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pp. 100--101
Abstract

5.1 POWER8 TM: A 12-core server-class processor in 22nm SOI with 7.6 Tb/s off-chip bandwidth
Fluhr, Eric J and Friedrich, Joshua and Dreps, Daniel and Zyuban, Victor and Still, Gregory and Gonzalez, Christopher and Hall, Allen and Hogenmiller, David and Malgioglio, Frank and Nett, Ryan and others
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pp. 96--97
Abstract

The POWER8 TM processor: Designed for big data, analytics, and cloud environments
Friedrich, Joshua and Le, Hung and Starke, William and Stuechli, Jeff and Sinharoy, Balaram and Fluhr, Eric J and Dreps, Daniel and Zyuban, Victor and Still, Gregory and Gonzalez, Christopher and others
IC Design & Technology (ICICDT), 2014 IEEE International Conference on, pp. 1--4
Abstract

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network
Zhou, Nancy Y and Restle, Phillip and Palumbo, Joseph and Kozhaya, Joseph and Qian, Haifeng and Li, Zhou and Alpert, Charles J and Sze, Cliff
System Level Interconnect Prediction (SLIP), 2014 ACM/IEEE International Workshop on, pp. 1--5
Abstract

Optimization and modeling of resonant clocking inductors for the POWER8 TM microprocessor
Groves, Robert and Restle, Phillip and Drake, Alan and Shan, David and Thomson, Michael
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the, pp. 1--4
Abstract


2013

On-chip circuit for measuring multi-GHz clock signal waveforms
Jenkins, Keith A and Restle, Phillip and Wang, PZ and Hogenmiller, D and Boerstler, D and Bucelot, T
VLSI Test Symposium (VTS), 2013 IEEE 31st, pp. 1--4
Abstract


2012

A shorted global clock design for multi-GHz 3D stacked chips
Pang, Liang-Teck and Restle, Phillip J and Wordeman, Matthew R and Silberman, Joel A and Franch, Robert L and Maier, Gary W
VLSI Circuits (VLSIC), 2012 Symposium on, pp. 170--171
Abstract

Subtractive Router for Tree-Driven-Grid Clocks
Haifeng Qian, Phillip J Restle, Joseph N Kozhaya, Clifford L Gunion
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 31(6), 868--877, IEEE, 2012


2011

Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus
Kozhaya, Joseph and Restle, Phillip and Qian, Haifeng
Proceedings of the International Conference on Computer-Aided Design, pp. 271--275, 2011
Abstract

POWER7™, a highly parallel, scalable multi-core high end server processor
Dieter F Wendel, Ron Kalla, James Warnock, Robert Cargnoni, Sam G Chu, Joachim G Clabes, Daniel Dreps, David Hrusecky, Josh Friedrich, Saiful Islam, others
Solid-State Circuits, IEEE Journal of 46(1), 145--161, IEEE, 2011


2009

A resonant global clock distribution for the cell broadband engine processor
Steven C Chan, Phillip J Restle, Thomas J Bucelot, John S Liberty, Stephen Weitzel, John M Keaty, Brian Flachs, Richard Volant, Peter Kapusta, Jeffrey S Zimmerman
Solid-State Circuits, IEEE Journal of 44(1), 64--72, IEEE, 2009

Ispd2009 clock network synthesis contest
Cliff N Sze, Phillip Restle, Gi-Joon Nam, Charles Alpert
Proceedings of the 2009 international symposium on Physical design, pp. 149--150


2007

Comparison of split-versus connected-core supplies in the POWER6 microprocessor
James, Norman and Restle, Phillip and Friedrich, Joshua and Huott, Bill and McCredie, Bradley
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 298--604
Abstract

On-chip timing uncertainty measurements on IBM microprocessors
R Franch, Phillip Restle, N James, W Huott, Joshua Friedrich, R Dixon, Steve Weitzel, K Van Goor, G Salem
Test Conference, 2007. ITC 2007. IEEE International, pp. 1--7

IBM POWER6 microprocessor physical design and design methodology
Rex Berridge, RM Averill, Arnold E Barish, Michael A Bowen, Peter J Camporese, Jack DiLullo, Peter E Dudley, Joachim Keinert, David W Lewis, Robert D Morel, others
IBM Journal of Research and Development 51(6), 685--714, IBM, 2007


2006

A 5GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor
Michael GR Thomson, Phillip J Restle, Norman K James
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, pp. 1522--1529

Distributed differential oscillators for global clock networks
Steven C Chan, Kenneth L Shepard, Phillip J Restle
Solid-State Circuits, IEEE Journal of 41(9), 2083--2094, IEEE, 2006


2005

New prospects for clocking synchronous and quasi-asynchronous systems
Restle, Phillip and Shepard, Ken
Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on, pp. xiii
Abstract

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
Lopez, Gerald G and Fiorenza, Giovanni and Bucelot, T and Restle, Phillip and Lanzerotti, Mary Yvonne
Proceedings of the 15th ACM Great Lakes symposium on VLSI, pp. 38--43, 2005
Abstract

Uniform-phase uniform-amplitude resonant-load global clock distributions
Steven C Chan, Kenneth L Shepard, Phillip J Restle
Solid-State Circuits, IEEE Journal of 40(1), 102--109, IEEE, 2005


2004

Design and implementation of the POWER5/spl trade/microprocessor
Clabes, Joachim and Friedrich, Joshua and Sweet, Mark and DiLullo, Jack and Chu, Sam and Plass, Donald and Dawson, James and Muench, Paul and Powell, Larry and Floyd, Michael and others
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 56--57
Abstract

Timing uncertainty measurements on the Power5 microprocessor
Phillip J Restle, Robert L Franch, Norman K James, William V Huott, Timothy M Skergan, Steven C Wilson, Nicole S Schwartz, Joachim G Clabes
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 354--355

A 4.6 GHz resonant global clock distribution network
Steven C Chan, Phillip J Restle, Kenneth L Shepard, Norman K James, Robert L Franch
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 342--343

Design and implementation of the POWER5™ microprocessor
Joachim Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald Plass, James Dawson, Paul Muench, Larry Powell, Michael Floyd, others
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, pp. 56--57


2003

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
Solid-State Circuits, IEEE Journal of 38(3), 457--463, IEEE, 2003

Design of resonant global clock distributions
Steven C Chan, Kenneth L Shepard, Phillip J Restle
Computer Design, 2003. Proceedings. 21st International Conference on, pp. 248--253


2002

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
Huang, Xuejue and Restle, Phillip and Bucelot, Thomas and Cao, Yu and King, Tsu-Jae
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002, pp. 19--22
Abstract

The clock distribution of the power4 microprocessor
Phillip J Restle, Craig A Carter, James P Eckhardt, Byron L Krauter, Bradley D McCredie, Keith A Jenkins, Alan J Weger, Anthony V Mule
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, pp. 144--145

The circuit and physical design of the POWER4 microprocessor
James D Warnock, John M Keaty, John Petrovick, Joachim G Clabes, Charles J Kircher, Byron L Krauter, Phillip J Restle, Brian A Zoric, Carl J Anderson
IBM Journal of Research and Development 46(1), 27--51, IBM, 2002


2001

Technical visualizations in VLSI design: visualization
Phillip J Restle
Proceedings of the 38th annual Design Automation Conference, pp. 494--499, 2001

Multi-GHz interconnect effects in microprocessors
Phillip J Restle, Albert E Ruehli, Steven G Walker
Proceedings of the 2001 international symposium on Physical design, pp. 93--97

Full-wave PEEC time-domain method for the modeling of on-chip interconnects
Phillip J Restle, Albert E Ruehli, Steven G Walker, George Papadopoulos
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 20(7), 877--886, IEEE, 2001

On-chip wiring design challenges for gigahertz operation
Alina Deutsch, Paul W Coteus, GERARD V Kopcsay, HOWARD H Smith, CHRISTOPHER W Surovic, BYRON L Krauter, DANIEL C Edelstein, PL Restle
Proceedings of the IEEE 89(4), 529--555, IEEE, 2001

A clock distribution network for microprocessors
Phillip J Restle, Timothy G McNamara, David A Webber, Peter J Camporese, Kwok F Eng, Keith A Jenkins, David H Allen, Michael J Rohn, Michael P Quaranta, David W Boerstler, others
Solid-State Circuits, IEEE Journal of 36(5), 792--799, IEEE, 2001

Physical design of a fourth-generation POWER GHz microprocessor
Carl J Anderson, J Petrovick, JM Keaty, J Warnock, G Nussbaum, JM Tendier, C Carter, S Chu, J Clabes, J DiLullo, others
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International, pp. 232--233


1999

Frequency-dependent crosstalk simulation for on-chip interconnections
Alina Deutsch, Howard H Smith, Christopher W Surovic, Gerard V Kopcsay, David A Webber, Paual W Coteus, George A Katopis, W Dale Becker, Allan H Dansky, George A Sai-Halasz, others
Advanced Packaging, IEEE Transactions on 22(3), 292--308, IEEE, 1999

Dealing with inductance in high-speed chip design
Phillip Restle, Albert Ruehli, Steven G Walker
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, pp. 904--909, 1999


1998

Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor
Phillip J Restle, KA Jenkins, A Deutsch, PW Cook
Solid-State Circuits, IEEE Journal of 33(4), 662--665, IEEE, 1998

Designing the best clock distribution network
Phillip J Restle, Alina Deutsch
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on, pp. 2--5


1997

A 400-MHz s/390 microprocessor
Charles F Webb, Carl J Anderson, Leon Sigal, Kenneth L Shepard, John S Liptay, James D Warnock, Brian Curran, Barry W Krumm, Mark D Mayo, Peter J Camporese, others
Solid-State Circuits, IEEE Journal of 32(11), 1665--1675, IEEE, 1997

When are transmission-line effects important for on-chip interconnections?
Alina Deutsch, Gerard V Kopcsay, Phillip J Restle, Howard H Smith, G Katopis, Wiren D Becker, Paul W Coteus, Christopher W Surovic, Barry J Rubin, Richard P Dunne Jr, others
Microwave Theory and Techniques, IEEE Transactions on 45(10), 1836--1846, IEEE, 1997


1994

SiGe-channel heterojunction p-MOSFET's
Sophie Verdonckt-Vandebroek, Emmanuel F Crabbe, Bernard S Meyerson, David L Harame, Phillip J Restle, Johannes MC Stork, Jeffrey B Johnson
Electron Devices, IEEE Transactions on 41(1), 90--101, IEEE, 1994


1993

Optimization of SiGe HBT technology for high speed analog and mixed-signal applications
DL Harame, JMC Stork, BS Meyerson, KY-J Hsu, J Cotte, KA Jenkins, JD Cressler, P Restle, EF Crabbe, S Subbanna, others
Electron Devices Meeting, 1993. IEDM'93. Technical Digest., International, pp. 71--74


1992

DRAM variable retention time
PJ Restle, JW Park, BF Lloyd
Electron Devices Meeting, 1992. IEDM'92. Technical Digest., International, pp. 807--810

A new'shift and ratio'method for MOSFET channel-length extraction
Yuan Taur, DS Zicherman, DR Lombardi, Phillip J Restle, CH Hsu, HI Nanafi, Matthew R Wordeman, Bijan Davari, Ghavam G Shahidi
Electron Device Letters, IEEE 13(5), 267--269, IEEE, 1992


1991

High-mobility modulation-doped SiGe-channel p-MOSFETs
Sophie Verdonckt-Vandebroek, Emmanuel F Crabbe, Bernard S Meyerson, David L Harame, Phillip J Restle, JMC Stork, Andrew C Megdanis, Carol L Stanis, Arthur A Bright, Gerrit MW Kroesen, others
Electron Device Letters, IEEE 12(8), 447--449, IEEE, 1991

High performance 0.25 $\mu$m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
VP Kesan, S Subbana, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, JA Ott
Electron Devices Meeting, 1991. IEDM'91. Technical Digest., International, pp. 25--28


1990

Internal probing of submicron FETs and photoemission using individual oxide traps
Phillip Restle, Antonio Gnudi
IBM journal of research and development 34(2.3), 227--242, IBM, 1990


1989

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces
TI Chappell, SE Schuster, BA Chappell, JW Allan, JY Sun, SP Klepner, SP Franch, PF Greier, PJ Restle
Solid-State Circuits, IEEE Journal of 24(4), 859--868, IEEE, 1989


1988

A 6.2 ns 64Kb CMOS RAM with ECL interfaces
TI Chappell, SE Schuster, BA Chappell, JW Allan, SP Klepner, RL Franch, PF Greier, PJ Restle
VLSI Circuits, 1988. Digest of Technical Papers., 1988 Symposium on, pp. 19--20

Individual oxide traps as probes into submicron devices
Phillip Restle
Applied physics letters 53(19), 1862--1864, AIP, 1988

Fast CMOS ECL receivers with 100-mV worst-case sensitivity
Barbara A Chappell, Terry I Chappell, Stanley E Schuster, Herman M Segmuller, James W Allan, Robert L Franch, Phillip J Restle
Solid-State Circuits, IEEE Journal of 23(1), 59--67, IEEE, 1988


1987

Design and experimental technology for 0.1-$\mu$m gate-length low-temperature operation FET's
George A Sai-Halasz, Matthew R Wordeman, DP Kern, E Ganin, S Rishton, DS Zicherman, H Schmid, Michael R Polcari, HY Ng, PJ Restle, others
Electron Device Letters, IEEE 8(10), 463--466, IEEE, 1987


1986

1/f noise in semiconductors and metals
Restle, Phillip John
Ph.D. Thesis, 1986
Abstract


1985

Non-Gaussian effects in 1/f noise in small silicon-on-sapphire resistors
PJ Restle, RJ Hamilton, MB Weissman, MS Love
Physical Review B 31(4), 2254, APS, 1985


1983

Thermally activated features in 1/f noise in silicon on sapphire
MB Weissman, RD Black, PJ Restle, T Ray
Physical Review B 27(2), 1428, APS, 1983


Nearly traceless 1/f noise in bismuth
RD Black, PJ Restle, MB Weissman
Physical review letters 51(16), 1476, APS, 1983